Interoperability with the Internet Protocol
The UDP/IP core implements the UDP/IPv4 standard RFC 768/791, including checksum, segmentation and reassembly hardware offload.
The UDP/IP core is tested for operation with popular FPGA vendors’ GbE Ethernet MACs.
Increase data transfer rates to 50/100/400 GbE without starting over
Allows for immediate operation at 10, 25 or 40 GbE, while providing a simple path to 50/100/400 GbE.
Offloads all UDP operations so you can work with datagrams
Offloads UDP standard RFC 768 from software to hardware.
L4 UDP Multicasts are pre-selected so that your application doesn’t have to perform this function
An integral IGMPv2 multicast pre-selector removes unwanted traffic.
10/25/40/50/100/400 GbE UDP Offload Engine FPGA IP Core – Datasheet
Concurrent datagram send and receive
Ethernet packet: programmable frame MTU up to 16K Bytes (Super-Jumbo Frame support)
UDP packet arbitrary datagram PDU up to IPv4 limit of 64K Bytes
16 Entry ARP cache (RFC 826)
ICMP (unsegmented echo response message type only, used by “ping”)
VLAN (IEEE 802.1Q) support
Layer 3 direct, allowing non-UDP application connectivity
Statistics accessible by control-plane interface
Low-Area implementation, allowing multiple core instances per FPGA
- Avalon and AXI4 interfaces