Arkville provides a high-throughput line-rate agnostic conduit between FPGA hardware and GPP software. Using industry-standard AXI interfaces on the FPGA side and DPDK interfaces on the software API/ABI side, Arkville provides an exceptional “out-of-the-box” solution for both hardware and software teams.
Because Arkville was designed with the specific goal of accelerating and empowering DPDK, the performance is significantly higher than one of a naïve DMA implementation on an FPGA.
Arkville SC16 Demo Showing RX/TX Plot.
Key Features and Benefits
Bring your FPGA-based packet processing solutions to market quickly
Future proof your GPP/FPGA application with the DPDK and AXI standards
Line rate agnostic: Operates at any line rate, including 1/5/10/25/40/50/100/400 GbE
Up to 150 Gbps and 120 Mpps with a contemporary PCIe Gen3x16 interface, Gen4 Ready
4 Physical Queue-Pairs (RX/TX) Standard; Up to 128 Physical Queue-Pairs
FPGA Vendor Agnostic RTL (works with Intel and Xilinx FPGAs)
Open-Source “net/ark” Arkville driver in DPDK 17.05 (see http://dpdk.org/dev/roadmap)
o Ready-to-Go Solution to FPGA/GPP Packet Movement
o 4 Physical Queue-Pairs (RX/TX) Standard; Up to 128 Physical Queue-Pairs
o Single PCIe Physical Function (PF) supporting multiple ports
o Concurrent, Full-Duplex Upstream and Downstream Data Movement
GPP / SOFTWARE SPECIFIC
o DPDK Arkville PMD in DPDK 17.05
o Tested extensively in with DPDK Test Suite (DTS)
o Unencumbered Application BAR (ABAR) for FPGA Application
FPGA / HARDWARE SPECIFIC
o AXI Streaming interfaces for packet movement
o Up to 256 Gbps, 500 Mpps burst traffic (Two 64 Byte wide, 250 MHz, AXI streams)
o Dedicated Application BAR (ABAR) AXI4-Master for the FPGA Application
o Integrated with Xilinx Vivado IP Integrator and Intel Quartus QSys
Click hereand fill out our contact form to request the
Atomic Rules Arkville GPP/FPGA Packet Mover IP Solution datasheet.
Atomic Rules is an electrical engineering consultancy based in Auburn, New Hampshire. We provide our clients with effective solutions to problems involving interconnection networks and reconfigurable computing. Our practice employs scalable, rule-based methods to tackle complex concurrency among heterogeneous processors.
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