Agenda

• Opinions on the state of FPGA/RC
  —What we see as the hard, high-value problems
• How AR operates
  —Quick to start, scale-on-demand
• A sampling of projects, partners, opportunities
  —SIGINT, OpenCPI, 4DSP, NetFPGA-10G

Agenda

• Opinions on the state of FPGA/RC
  —What we see as the hard, high-value problems
• How AR operates
  —Quick to start, scale-on-demand
• A sampling of projects, partners, opportunities
  —SIGINT, OpenCPI, 4DSP, NetFPGA-10G

Familiar, Recurring Problems

• RTL design for FPGA SoC is (still) painful
  —Too Brittle, Too Costly; yet widely practiced
  —Not going away
  —Inadequate emphasis on Platform-Based design
  —Weak methodologies for complex-concurrency
  —Alternatives can be encumbered by FUD
  • Requires a show-me solution: "prove it"
  • Requires strong standards alongside

"Pick and Shovel" RTL

• FPGA::RTL complexity overload
  —Implicit signal assumptions are time-bombs
  —Clock-cycle reasoning at the system level is crazy
  —The RTL verification burden is unsustainable
• Standard Interfaces (e.g. AXI, OCP-IP) help
  —Provide Explicit signaling rules

Specialized Heterogeneity

• FPGA no longer just a sea of k-LUTS and DFFs
  —Understand why: Trimberger – FPL2007
• Hardcores for DSP, BRAM, EMAC, PCIe, ARM
• Rapidly "Going Deep" is a highly-valued
• Atomic Rules sees this opportunity!
  —Make the "hard" problems appear "simple"
  —Examples (RF/PSD in JCREW; TL µNoC in OpenCPI)

Important Points

• We have shown transactional methods can be superior to RTL in delivering productivity, quality, and time-to-solution
• We do not claim that we have a better approach over all problem spaces (we don't)
• We tackle Complex Concurrency

Segue

[Atomic Rules RF Bench]

Agenda

• Opinions on the state of FPGA/RC
  —What we see as the hard, high-value problems
• How AR operates
  —Quick to start, scale-on-demand
• A sampling of projects, partners, opportunities
  —SIGINT, OpenCPI, 4DSP, NetFPGA-10G

Application and Implementation

• We separate concerns between the application and the implementation
• IP codes are written functionally; describing state, and the functions which act upon it
• Application is insulated from implementation, but not oblivious to it
• We preserve the value in legacy RTL tools and process; but don't champion their use

Our Broad Values

• We know Signals and Systems
• We know Complex Concurrency
  to offer our clients...
• More with less, in less time
• Fewer defects: Correct-by-Construction
• Productivity, time-to-solution
• Reduced cost of reuse and tech refresh

Our Challenges

• Scale-on-Demand: we're ready
  —Dialogs with FPGA/RC professors, grad-students
  —Using IEEE, ACM events to recruit
• Choosing the right clients and vendors is hard
  —Lots of "pick and shovel" (but not our bailiwick)
• Understanding partner's needs takes time...
  —And we embrace this challenge

Segue

[4DSP FMC108 Module at Atomic Rules – July 2010]

Agenda

• Opinions on the state of FPGA/RC
  —What we see as the hard, high-value problems
• How AR operates
  —Quick to start, scale-on-demand
• A sampling of projects, partners, opportunities
  —SIGINT, OpenCPI, 4DSP, NetFPGA-10G

RADAR and SIGINT

• Complex, multiple FPGA + GPP
• Built with OpenCPI Infrastructure
  —more on this later
• Plenty of Application math
  —FFTs
  —Complex Arithmetic
  —DUC/DDC

Montage from RADAR/SIGINT effort – CY2010

Component Portability Infrastructure

• OpenCPI is an open-source middleware
• Focus is on IP Portability, GPP/FPGA/GPU
• Level the playing field: IP that "Travels"
• www.opencpi.org went live CY2009
• HDL on IEEE VHDL/Verilog platform
• Most codes are open-sourced under LGPL3
• AFRL awarded MFS $970K in Q4-CY2010

4DSP

• Proven provider of FMC modules
• AR: growing the FMC Ecosystem with BSV
• Everything 4DSP has shown looks great
• Ball in AR's court to roll into OpenCPI
• Come to FCCM-2011 (May 1-3, SLC, UT)

4DSP Modules at Atomic Rules, Auburn

For development, testing, and integration into OpenCPI

4DSP FMC150

4DSP FMC108 on ML605

NetFPGA-10G

• Research Platform for 10GbE +
• Collaboration with Xilinx and Stanford
• DMA "OPED":

NetFPGA-10G team at Xilinx Dublin

Summary

• We've shown
  —Opinions on the state of FPGA/RC
  —A little bit about how AR operates
  —A sampling of projects, partners, opportunities
• Let's Talk, Thanks!