Atomic Rules announces DPDK-aware FPGA/GPP data mover

Atomic Rules announces DPDK-aware FPGA/GPP data mover

Systems requiring Linux kernel bypass can now offload server cycles to FPGA gates

AUBURN, NH – Atomic Rules, a reconfigurable computing IP firm, is pleased to announce the launch of Arkville, a DPDK-aware FPGA/GPP data mover enabling Linux DPDK applications to offload server cycles to FPGA gates.

“Our Arkville launch brings five man-years of DPDK-first passion to market,” said Shepard Siegel, CTO of Atomic Rules. “By introducing Arkville, Atomic Rules is enabling Linux DPDK applications that seek acceleration in a software-first fashion to offload server cycles to FPGA gates. This allows project managers to bring their product to market faster and focus on differentiating their product by not having to re-invent a GPP/FPGA packet mover.”

Arkville is a combination of a DPDK PMD that runs on a GPP and an RTL IP Core that runs on an FPGA. Using industry-standard AXI interfaces on the FPGA side and DPDK interfaces on the software API/ABI side, Arkville provides an exceptional “out-of-the-box” solution for both hardware and software teams.

Learn more: Arkville DPDK-aware FPGA/GPP data mover

Atomic Rules Arkville IP core operates at any line rate, including 1/5/10/25/40/50/100/400 GbE, and works with most popular, high-performance FPGAs. Atomic Rules has contributed the Arkville Poll Mode Driver (PMD) code to the DPDK Project of The Linux Foundation under the terms of the BSD 3-Clause open source license. Arkville achieves up to 150 Gbps and 120 Mpps with a contemporary PCIe Gen3x16 interface, and is also Gen4 Ready. Because Arkville was designed with the specific goal of accelerating and empowering DPDK, the performance is significantly higher than one of a naïve DMA implementation on an FPGA.

Industry Support For Arkville

“We are pleased to now offer Arkville as an IP core to our FPGA board customers in addition to already using it as the PCIe data mover in our new Stream family of network products,” said Craig Lund, Vice President of Network Products at BittWare. “We’ve noted early interest in Arkville as it fits with a wide range of applications.”

“We were impressed at how easily Arkville ported on our product, and are pleased that Atomic Rules is offering a DPDK solution available to our customers”, said Adam Smith, CEO at Alpha Data Inc. “We believe offloading server cycles to FPGA gates opens the door to new opportunities for systems requiring Linux kernel bypass.”

Community Support

“Since April, the DPDK community and The Linux Foundation have worked to establish a governance structure for the DPDK Project to nurture a vibrant and open community” said Mike Woster, COO at The Linux Foundation “Atomic Rules’s launch of Arkville is a good example of how an open governance structure can help foster open innovation.”

Arkville IP Core Pricing and Availability

The Atomic Rules Arkville DPDK-aware FPGA/GPP data mover IP core is available for purchase. Arkville includes 1×100 GbE and 4×10 GbE examples as starting points for development. Contact us for pricing information.

About Atomic Rules

Atomic Rules is an electrical engineering consultancy providing its clients with effective solutions to problems involving interconnection networks and reconfigurable computing. Their practice employs scalable, rule-based methods to tackle complex concurrency among heterogeneous processors. Atomic Rules understands the limitations of composing complex processor interactions using conventional RTL methods. To address this challenge, they use tools and techniques inspired by functional programming. Beyond RTLs, they specialize in creating source codes written in Bluespec SystemVerilog, a vehicle for code correctness, portability and reuse. Atomic Rules provides its clients with expert SoC/FPGA competencies that build upon RTL/ESL design and verification techniques – not reinvent them. For more information, visit www.atomicrules.com.

About Alpha Data

Established in 1993, Alpha Data is a world leader in high performance Xilinx FPGA based plug-in acceleration boards for Data Center and high-performance computing applications including video processing, machine learning, and network acceleration. Alpha Data’s low-cost, power-efficient accelerators leverage Xilinx’s All Programmable FPGAs and the SDAccel development environment for Open CL, C and C++ to accelerate processing, increase data throughput, and deliver power optimized solutions for computing clusters. Designed to be server-friendly for large scale data center deployment, Alpha Data’s range of FPGA accelerator boards are all in a low-profile PCIe format with passive cooling. Alpha Data’s high-reliability hardware platforms are ideal for development as well as full-scale production deployment. For more information on Alpha Data, visit www.alpha-data.com.

About BittWare

Since 1989, BittWare has designed and manufactured high-end computing solutions for the most demanding government and commercial applications. Today, BittWare’s FPGA PCIe boards target high-performance users who need 100G networking (such as on our Xilinx UltraScale+ boards), OpenCL support (such as with our A10PL4 with an Intel Arria 10), and memory options, including 256GB DDR4, QDR-II+, and Hybrid Memory Cube. Low-profile and full-size boards with active or passive cooling are available, along with a range of enclosures, software tools, and IP cores. For customers with custom needs, our ODM solutions leverage BittWare’s extensive design experience and top manufacturing partnerships. Learn more at www.BittWare.com .

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The Linux Foundation has registered trademarks and uses trademarks. For a list of trademarks of The Linux Foundation, please see its trademark usage page: https://www.linuxfoundation.org/trademark-usage. Linux is a registered trademark of Linus Torvalds.

Atomic Rules joins Amazon F1 Partners Network

Atomic Rules joins Amazon F1 Partners Network – now offering design services to clients seeking an F1 cloud presence!

For more information, please see: Amazon EC2 F1 Instances, Customizable FPGAs for Hardware Acceleration Are Now Generally Available

Amazon EC2 F1 Consulting Services

 

Atomic Rules is proud to become a member of The Linux Foundation

Atomic Rules is proud to become a member of The Linux Foundation alongside ARM, AT&T, Cavium, Intel, NXP, Red Hat, ZTE Corporation, 6WIND, Huawei, Spirent, Wind River, KAIST, University of Limerick, University of Massachusetts Lowell, and Tsinghua University.

Click to access the official Linux Foundation press release.

LFdownload

 

100GbE and PCIe Gen3 x16 demo – leveraging DPDK for FPGA+CPU computational packet processing

Xilinx, BittWare, and Atomic Rules leveraging Intel Corporation’s DPDK to achieve 150Gbps line rate on mixed FPGA/CPU architecture.

Click to access Xilinx Xcell Daily blog for more details.

atomicrules_dpdk_demo

Atomic Rules COTS Journal Article: Internet Transport Protocols Contend for Military Interconnect Role

Think UDP is lossy? Atomic Rules shows how transceivers tech evolution disrupts this legacy assumption. UDP now a serious contender in multicomputer interconnect when costs and time-to-deployment are key concerns (click below to see military radar use case on page 17).

BittWare and Atomic Rules announce an FPGA-based UDP Offload Engine IP Core for 10/25/50/100 GbE

Hardware-based acceleration dramatically improves throughput and provides a simple path to 50 and 100 GbE.

CONCORD, NH & WASHINGTON D.C. – BittWare, a premier FPGA board supplier for over 25 years, has collaborated with Atomic Rules, a reconfigurable computing IP firm, to announce a UDP Offload Engine (UOE) IP core today at the FCCM 2016 Symposium.  A live demo running on BittWare’s XUSP3S PCIe board showcases the UOE IP core operating at 25 GbE with no packet loss.

Atomic Rules UOE IP core operates at 10/25 GbE and is upgradable to 50/100 GbE for recent Xilinx and Altera-based BittWare platforms. The UOE IP core optimizes throughput for all line rates, with no packet loss even for very small packets. It also offers support for Super Jumbo Frames and robust multicast capabilities. The combination of BittWare capabilities and UOE provides clients with a cost effective, cutting edge set of capabilities in hardware that leverage the RFC 768 standard, including simultaneous transmit/receive, checksum, and segmentation.

The UOE IP core enables application-level UDP datagrams to be concurrently sent and received on a LAN or across a network. An integral IGMPv2 multicast pre-selector removes unwanted traffic, and L4 UDP multicasts are pre-selected so that user applications don’t have to perform this function. The UOE IP core is tested for operation with popular FPGA vendors’ 10 GbE and 25 GbE MACs.

Learn more: UDP Offload Engine

“We’re pleased to be able to work with Atomic Rules to add this innovative application IP to our already well established FPGA platforms,” said Ron Huizen, Vice President of Systems & Solutions at BittWare. “Their ability to run 25 GbE today with an easy upgrade path to 100GbE is a real benefit for our customers.”

“Developers have their eye on 50 and 100 GbE,” said Shepard Siegel, CTO of Atomic Rules. “They want to start now with 10 and 25 GbE but also to make sure their effort is sustainable. Our UDP Offload Engine gives them the best of both worlds, providing them maximum throughput now with existing hardware and a straightforward upgrade as network speeds increase.”

UDP Offload Engine IP Core Pricing and Availability

The Atomic Rules UDP Offload Engine IP core is available for purchase. Contact us now for pricing information.

About Atomic Rules

Atomic Rules is an electrical engineering consultancy providing its clients with effective solutions to problems involving interconnection networks and reconfigurable computing. Their practice employs scalable, rule-based methods to tackle complex concurrency among heterogeneous processors. Atomic Rules understands the limitations of composing complex processor interactions using conventional RTL methods. To address this challenge, they use tools and techniques inspired by functional programming. Beyond RTLs, they specialize in creating source codes written in Bluespec SystemVerilog, a vehicle for code correctness, portability and reuse. Atomic Rules provides its clients with expert SoC/FPGA competencies that build upon RTL/ESL design and verification techniques – not reinvent them. For more information, visit www.atomicrules.com.

About BittWare, Inc.

For over 25 years, BittWare has designed and deployed high-end network processing, signal processing, and high performance computing platforms that significantly reduce technology risk and time-to revenue for our OEM customers. Our products utilize the latest FPGA technologies on industry-standard COTS form factors, including PCIe, and are available either as boards or in boxes. We also provide a great deal of value-add with IP, software, support, and services. When customer requirements make it difficult to use industry-standard boards, BittWare can provide modified solutions and/or licensed designs. For more information on BittWare and its innovative FPGA COTS solutions, visit www.bittware.com.

FPL 2016

Atomic Rules is again pleased to be a sponsor of…

The 26th International Conference on Field-Programmable Logic
August 29 – September 2, 2016
Lausanne, Switzerland

http://fpl2016.org

FPGA 2016

Atomic Rules is again pleased to be a sponsor of…

24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
February 21-23, 2016
Monterey, California

http://www.isfpga.org/

FCCM ­2016

Atomic Rules is again pleased to be a sponsor of…

The 24th IEEE International Symposium on Field-Programmable Custom Computing Machines
May 1-3, 2016
Washington, DC

http://fccm.org/2016/