Xilinx, BittWare, and Atomic Rules leveraging Intel Corporation’s DPDK to achieve 150Gbps line rate on mixed FPGA/CPU architecture.
News & Events
- 100GbE and PCIe Gen3 x16 demo – leveraging DPDK for FPGA+CPU computational packet processingNovember 22, 2016 - 2:16 pm
Xilinx, BittWare, and Atomic Rules leveraging Intel Corporation’s DPDK to achieve 150Gbps line rate on mixed FPGA/CPU architecture. Click to access Xilinx Xcell Daily blog for more details.
- Atomic Rules COTS Journal Article: Internet Transport Protocols Contend for Military Interconnect RoleNovember 22, 2016 - 2:10 pm
Think UDP is lossy? Atomic Rules shows how transceivers tech evolution disrupts this legacy assumption. UDP now a serious contender in multicomputer interconnect when costs and time-to-deployment are key concerns (click below to see military radar use case on page 17).
- BittWare and Atomic Rules announce an FPGA-based UDP Offload Engine IP Core for 10/25/50/100 GbEMay 2, 2016 - 10:36 am
Hardware-based acceleration dramatically improves throughput and provides a simple path to 50 and 100 GbE. CONCORD, NH & WASHINGTON D.C. – BittWare, a premier FPGA board supplier for over 25 years, has collaborated with Atomic Rules, a reconfigurable computing IP firm, to announce a UDP Offload Engine (UOE) IP core today at the FCCM 2016 Symposium. […]